The present invention generally relates to flipchip bump patterns, and more specifically relates to a flipchip bump pattern where power and ground bumps are disposed in striped configuration.
Flipchip packaging provides that the active area of a chip is flipped over in the package, facing downward. Instead of facing up and being bonded to package leads with wires from outside edges of the chip, flipchip packaging provides that any surface area of the flip chip can be used for interconnection, which is typically effected using metal bumps of solder, copper or nickel/gold. These “bumps” or “balls” are soldered to the package substrate or the circuit board itself and underfilled with epoxy. Flipchip packaging allows for a large number of interconnects with shorter distances than wire, which greatly reduces inductance.
Traditional flipchip configurations require a dedicated silicon layer to create flipchip core power and ground bumps as well as bussing (for both the power and the ground). As a result, this layer cannot be used for core signal routing.
FIG. 1 illustrates a typical prior art flipchip die section or layer 10 (i.e., the top-most metal layer). Reference numerals 12 indicate core power bumps (i.e, each circle with a “+” therein is a core power bump), while reference numerals 14 indicate core ground bumps (i.e, each circle with a “−” therein is a core ground bump). As shown, the flipchip core power bumps 12 and the ground bumps 14 are arranged in an alternating fashion (i.e., power bump 12, ground bump 14, power bump 12, ground bump 14, etc.). Power mesh bussing 16 is also built on this layer, and is placed between the bumps 12, 14.
FIG. 2 provides an enlarged view of a portion of the section 10 shown in FIG. 1. As shown, mesh trunks 16 are strapped to the appropriate core power bumps 12 or ground bumps 14 in an alternating fashion. Reference numeral 18 identifies mesh core power busses, while reference numeral 20 identifies mesh core ground busses. Metal extension tabs 22 are used to connect the bumps 12, 14 to the appropriate busses 18, 20—i.e., power bumps 12 are connected to a power bus 18, and ground bumps 14 are connected to a ground bus 20.
Reference numerals 24 in both FIGS. 1 and 2 identify metal bussing which is provided on one or more other layers, such as the next or second top-most metal layer. This bussing 24 is conductively connected to the power busses 18 and ground busses 20 on the top-most metal layer 10 to provide a uniform current distribution across the die. It should be noted that the orientation of the top-most and second top-most metal layers (i.e., the busses 18, 20, 24) can be rotated ninety degrees depending on the application and the preferred routing directions.
While the scheme illustrated in FIGS. 1 and 2 and described hereinabove enables a power distribution method across the die, the scheme presents some disadvantages.
First, the scheme provides that the top-most metal layer is fully utilized, thereby reducing signal routing resources. Specifically, due to the bump arrangement (i.e., power bump 12, ground bump 14, power bump 12, ground bump 14, etc. in alternating fashion), power mesh layers 16 (18 and 20) must be placed between bumps and this prevents any horizontal or vertical signal routing to be placed on this top-most metal layer. Since this top-most metal layer is fully utilized for flipchip power distribution, additional metal layers are required to route the design.
Second, the metal extension tabs 22 which are required to connect the bumps 12, 14 to the busses 18, 20 result in voltage drops as well as electromigration considerations. Specifically, a finite voltage drop occurs across the metal extension tabs 22. This contributes to an overall IR drop across the chip which must be compensated for by adding more metal or reducing chip power. Furthermore, the metal extension tabs 22 must be sufficiently wide to carry suitable current. This contributes to an increase in the metal density of this top-most metal layer which has a finite manufacturing limit. Hence, metal must be removed from other sections of the power mesh to meet design rule specifications.
Third, the bump arrangement (i.e., power bump 12, ground bump 14, power bump 12, ground bump 14, etc. in alternating fashion) compromises package plane electrical performance. Specifically, core power bumps 12 and ground bumps 14 must be connected within the package to appropriate power and ground planes, and the alternating configuration of the bumps necessitates creating via holes in the package power planes to escape these bumps. This reduces the electrical performance of the package power and ground planes, mostly as a consequence of increased inductance.